Tempus is a response to the growth in number of timing views that design teams have seen over the past decade caused by a combination of nanometre-process effects and the need to support many different power modes to save energy.

“Low power is important across all markets and we are seeing more design complexity. The number of modes that have to be analyzed is increasing. As a result the time taken for design closure is increasing. Timing signoff is taking as much as 40 per cent of the implementation flow at 20nm,” said Anirudh Devgan, corporate vice president for silicon signoff and verification in Cadence’s silicon realization group.

The current problem with signoff is that the iterations needed to make a design close timing have become increasingly onerous, partly because the analyses and fixes remain decoupled. The Tempus tool brings in optimizations from the company’s Encounter suite to fix violations within the timing tool itself rather than forcing them to be done as ECOs in the implementation tools for the fixes then to be re-analyzed within the timing tool to check that they perform as expected, which is not always the case.

“We can do design closure activities that used to take two to three weeks previously in a few days using Tempus,” said Devgan.

As well as performing fixes, Tempus introduces two techniques. One is to reduce the amount of time it takes to generate the views themselves.

“There already was some parallelism using in timing analysis, but these designs are huge. So the parallelism required is massive parallelism,” Devgan said. “We can share memory across multiple machines. The way that the parallelism is achieved, it runs well across machines interconnected by 1Gb/s Ethernet and they do not need to be very high performance. There are a lot of cheap machines already used in simulation farms that have 128Gbyte of memory each that run well with Tempus, so users can reuse that resource for faster timing closure.

“We have seen a 10x performance improvement through parallelization,” Devgan added.

The second change is the introduction of path-based analysis to improve the overall accuracy of timing, particularly for critical paths. Excessive guardbanding using traditional graph-based approaches has made it difficult to close timing for critical paths. Path-based techniques make it possible to claw back performance. Devgan said the path-based algorithms are, on average, 3 per cent more accurate than existing techniques.

“That 3 per cent can be used to close timing more quickly or used to recover power,” Devgan claimed.

Path-based analysis is more compute intensive than graph-based but improved algorithms to ensure that the correct paths are analyzed and the addiitonal of massive parallelism makes it feasible now, according to Cadence.

“The typical workflow would be to run graph-based analysis first and then run path-based on the critical paths,” Devgan explained.

Sanjive Agarwala, director of processor development at Texas Instruments, said: “As we move to more advanced process nodes, timing closure becomes more difficult. It’s great to see Cadence taking on this challenge by offering new technology designed to tackle tough design closure issues.”

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The TVS verification IP provides access to the source code and tests that are mapped to the protocol specification so that the user can see the intention of the test. The asureVIP library components contain traffic generators that allows the chip integrator to generate traffic across the interface. Synthesisable drivers and C interfaces allow the VIP to be used in emulation using SCEMI.

Protocols handled by the verification IP components include the MIPI RFFE and DSI interfaces, the I2C and SPI serial buses, Ethernet networking and PCIExpress and USB 3.0 high-speed I/O channels.

Mike Bartley, CEO of TVS, said, “We have been working with clients on our VIP for some time now and a lot of the VIP is proven in a number of different environments and in silicon.”

TVS wrote the UVM-compliant verification IP components in native System Verilog. TVS said it is able to provide customized VIP “under flexible ownership arrangements”. The TVS agile development process also means that the verification IP is delivered in a number of short ‘sprints’ to allow an early start on verification.

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The UK’s Technology Strategy Board has decided to give SureCore one of its SMART awards for the development of a demonstrator chip that will be used to test the company’s array control and sensing scheme. The company claims its approach will lower active power consumption and is working with foundries on FD-SOI (Guide)  and finFET (Guide) implementations.

The company has used statistical modelling – one of its directors is leading variability and statistical modelling researcher Professor Asen Asenov – to develop the SRAM IP and come up with a way of lowering powery consumption, which SureCore claims will be less than half that of existing approaches.

Paul Wells, CEO of SureCore, said: “We have proven the technology in simulation but to fully characterise and demonstrate its benefits implementation in silicon is a must. This is a critical next step in demonstrating the value of our IP to our customers.”

The post SureCore picks up grant for low-power, nanometer SRAM IP appeared first on Tech Design Forum.

Jeff Waters, general manager of the military, industrial and computing division of Altera, explained on a conference call with analysts: “The need for Altera to get more directly into power management can best be explained by a meeting we had with a European customer last year. We were reviewing a design and they were excited about the integration they could achieve. They could integrate a DSP chip, a few microcontrollers as well as an interface ASSP. The director for the group then drew a large square around the periphery of our product that and told us it represented the area taken up by the 20-plus chips and passive components that made up the power supply.

“Helping to simplify that would be the next challenge that we could solve. It seemed like a clear opporunity for Altera to do more for its customers in an area of critical need,” Waters added.

Part of the problem for FPGA makers such as Altera is the rate at which they have integrated logic and analog interfaces, such as serial interfaces, onchip. “Over the life of the Stratix family, we have achieved a 20-times gain in logic density. With this extra capacity, the number of power supplies needed has grown from nine to twenty four,” Waters said, adding that Enpirion has been able to use integration to produce much smaller power-supply devices that are able to power complex FPGAs.

Waters said one advantage of the Enpirion technology lies in its approach to providing power to sensitive analog subsystems, such as the transceivers used on the Arria and Stratix parts. “Traditionally, those are made using old technology LDOs [low dropout regulators]. It’s necessary to do that because of their noise performance. Enpirion claimed they could achieve similar noise performance using a switching regulator, with which you get much better power efficiency. You get about 50 per cent greater power savings but it was not something you could achieve traditionally because of the noise performance. We found Enpirion could get very clean behavior from their design.”

Although Altera expects to continue working with other power-management suppliers on discrete designs, Waters said: “In the future, you will see a lot more dynamic power management, where you will see us differentiate and provide much greater levels of power reduction.”

The acquisition reflects the uphill struggle that independent startups face when trying to gain a foothold in the market. During a dinner with the customer from a tier-one enterprise hardware maker, Waters found out that the preferred power-management supplier for one design was Enpirion. “His team were unable to meet key specifications using traditonal suppliers. They came across Enpirion and convinced corporate procurement to specify them despite the [small] size of the company. He was convinced they would be scooped up by a larger company.”

As Altera and Enpirion sell into similar markets, such as telecom infrastructure, industrial and enterprise systems, the acquisition provides the opportunity for buyers to reduce the number of suppliers. Waters said among its customers, Altera is often in the top group of suppliers measured by spend. “They would like to consolidate spending among their top suppliers.”

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The flow integrates DeFacTo’s SIGNOFF DFT tool with Real Intent’s Meridian CDC.

SIGNOFF makes it possible to do DFT analysis and enhancements earlier in the design process, at the block, IP core, and top levels of the chip’s hierarchy. It can also be used to explore DFT strategies such as test compression, memory/logic BIST and JTAG.

Meridian CDC uses structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASICs or FPGAs are received reliably. The company says the tool can handle designs of more than 500 million gates.

Hamed Emami, vice president of worldwide sales at Real Intent, said in a statement, “DeFacTo offers unique technology for testability sign-off at the pre-synthesis stage of design. By partnering with DeFacTo, we bring design teams the best platforms in the market for RTL sign-off for both DFT and CDC issues.”

Dr. Chouki Aktouf, founder, president and CEO of DeFacTo, added, “Our collaboration with Real Intent is a natural outcome of our complementary product offerings that help eliminate complex failure modes of SoCs at the RTL stage of design.”

The joint flow will be on show in DeFacTo’s booth (#409) and Real Intent’s booth (#1031) at the Design Automation Conference, in Austin, Texas, next month.

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The JasperGold Low Power Verification App addresses designs with multiple voltage and power-management domains at the RTL.

It reads the RTL description and creates an internal power-aware formal model based on the power partitioning specifications. This is used to verify power optimization structures, management circuitry, and sequencing. Then, when applied with other Apps it verifies that power optimizations have not corrupted the original functionality.

An important target – and where Jasper Design Automation reckons it has some differentiation – is figuring out whether or not the spec and functionality are still met once the power management circuity has gone into a design. Often, this stage is especially vulnerable.

The App also inserts power supply network, switches, isolation cells, and data retention cells into the internal model. It then extracts power sequencing information from the power specification and infers a sequence of power control events necessary to implement the power-up or power-down correctly.

App integration and collaboration

The App concept is an interesting one. Jasper Design Automation has taken the vision a little further than simply modules.

The main technical components are the various formal packages available, a common and shared database and an architecture that allows data to be shared across different Apps. The tools themselves can operate simultaneously or undergo multiple individual invocations.

So buy what you need for your design – application specific tooling, in essence. But you can also virtualize the operation across server farms, very useful given that many SoCs today are designed and verified in multiple locations.

And, of course, each new App arrives with a ready-made, plug-in market. Not a bad spin on iTunedas.

The latest low power App is available immediately and Jasper will be demonstrating that alongside the rest of the family at DAC. In addition to the new launch, these include:

• Formal Property Verification App
• Connectivity Verification App
• X-Propagation Verification App
• RTL Development App
• Architectural Modeling App
• Behavioral Property Synthesis App
• Structural Property Synthesis App
• Control and Status Register Verification App

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So, as the new launch provides evidence that the pre-DAC announcement flow is building, here are the key points.

• Power: Forte is adding three new tuning knobs for optimization across datapaths, registers, clock trees and memory.
• Architecture: The company has developed a new one for its synthesis core that combines scheduling and allocation for enhanced performance.
• SystemC: An updated Cynthesizer IDE is aimed at both advanced and newbie users, and also includes ‘kick-starters’, essentially pre-defined templates that users tweak according to their requirements.

Here’s a little more on each in turn.

Power

There’s more and more discussion of taking power optimization up to the system level. As Forte themselves point out, “you can automate complex low power optimizations often difficult or impossible to realize with hand-written RTL code.”

Moreover at DATE, Docea Power talked about the rise of the power architect, a design manager working at the architectural level to define goals, set constraints and introduce enhancements as early as possible. Forte also wants his or her attention. So, how are they tugging your coat?

Specifically, the three new Cynthesizer 5 optimization knobs are:

1. HLS-optimized clock gating to analyze microarchitectures and identify optimization opportunities that would not be self-evident in RTL.
2. Finite state machine optimization to minimize power there and also that consumed by false switching in the datapath.
3. Memory-targeted features to optimize accesses for performance or power.

We’re waiting on some customer stories here, but Forte says the combination of the three features can deliver power reductions of up to 60%.

Cynthesizer Architecture

Forte is obviously leveraging both performance and result benefits by now combining scheduling and allocation within the latest C5 synthesis core.

Part of that includes a new raft of scheduling algorithms aimed at speeding up the architectural analysis and delivering optimization options for the appropriate combination of power, performance and area.

On area specifically, Forte says Cynthesizer 5 typically delivers a 9% improvement against previous releases.

Again, it will be interesting to hear a bit more about how this has played out during beta.

SystemC

No-one could question how hard Forte has banged the drum on ESL and SystemC. For years.

But there is still a gap between, say, Asia (particularly Japan) and Europe on one side, and North America on the other in terms of adoption. It isn’t the yawning gulf it once was, but it’s still there.

So, the Cynthesizer 5 enhancements aimed at making SystemC easier-to-use are worth noting. Its SystemC IDE is specifically aimed at all levels of expertise. But beyond that, it’s the templates that catch your interest.

We’re already seeing much the same in, say, virtual prototyping, where Synopsys provides similar building blocks within its Virtualizer environments. They sell the concept to newer (or more conservative) adopters. Meanwhile, for those already familiar with ESL, they take away much of the early-stage drudgery and allow them to get started earlier on optimization and differentiation.

Beyond that, Forte says that the Cynthesizer Workbench has been redesigned to allow faster design, debug, and analysis of SystemC models and the resulting RTL designs. The analysis environment includes SystemC and RTL source linking, waveforms, and other tools to optimize design results.

Overall, the Cynthesizer 5 launch is eye-catching because it seems well in tune with where the market is heading and what it wants. Simplification and modularization of ESL makes a lot of sense, saving time and selling the possibilities. System-level power analysis is gaining traction fast. And, of course, Forte says it’s made what the tools already do faster and better.

The real proof will come with the demos. These start at DAC in Austin and, if attending, you can request one.

The post Forte Cynthesizer aims at performance, power and ease of use appeared first on Tech Design Forum.

However, you can still get an exhibits-only pass for nothing, as long as you register for the ‘I Love DAC’ scheme before Friday, May 17th. That’s just three days from now.

Once the offer expires, DAC 2013 exhibits-only registration will cost $65. That’s either in advance or on-the-day.

The scheme is sponsored by three EDA vendors (Atrenta, Forte and Jasper), and will give you a three-day pass to the DAC 2013 exhibit floor and main keynotes.

It’s a risky move. This is DAC’s 50th anniversary year, and that has undoubtedly raised its profile. However, this is also the first time that the conference has been held in Austin, Texas.

Organizers have worked hard to encourage the city’s many engineers to turn up in force, but some twitchiness always goes with a new venue. Exhibitors will be watching closely to see if abandoning Free Monday discourages last-minute and casual traffic – and what kind.

A typical engineer’s workload is such that he or she often cannot commit to going to a show until the day itself – though obviously technical conference attendance is more formally planned.

Either way, it is what it is. To get a free ‘I Love DAC’ pass click the link below and follow the instructions, as we said above, before Friday, May 17th.

I don’t want to pay $65 for a DAC 2013 exhibit pass.

Meanwhile, here’s another quick recap of our DAC preview articles.

DAC 2013 Preview I: Putting users first and marking 50 years

DAC 2013 Preview II: Panels

DAC 2013 Preview III: Embedded

DAC 2013 Preview IV: Management and Training Days

DAC 2013 Preview V: Rounding out the keynotes

DAC 2013 Preview VI: CEO ‘visions’ added

The post DAC 2013 REMINDER: ‘No Free Monday’ appeared first on Tech Design Forum.

First up is Mentor’s Wally Rhines, who’ll precede the Monday, June 3rd morning keynote (Freescale Semiconductor’s Gregg Lowe) at 9.15am.

Next is Cadence’s Lip-Bu Tan. He will speak before the Monday, June 3rd afternoon keynote (National Instruments’ James Truchard) at 4.00pm.

Synopsys’ Aart de Geus will speak before the Tuesday, June 4th morning keynote (Samsung’s Stephen Woo) at 9.15am.

Finally, Jasper’s Kathryn Kranen will offer her views before the Thursday, June 6th morning keynote (Professor Alberto Sangiovanni-Vincentelli) at 11.00am.

The speeches mark DAC’s 50th anniversary and will give the four leading industry lights the chance to outline – albeit briefly – their visions for what will define the next half-century in technology and design. All will take place in Ballroom ABC at the Austin Convention Center.

It ain’t quite the CEO Panel so popular at DACs past. Though that has, for many, found a perfectly adequate replacement in John Cooley’s ‘Troublemakers’ session. That carving of raw meat has this year also been scheduled on Monday, June 3rd at 3.00pm, this time in Ballroom C.

John’s DAC 2013 line up includes Oasys Design System’s Joe Costello, IC Manage’s Dean Drako, Atrenta’s Mike Gianfagna, and Mentor’s Joe Sawicki as well as Jim Hogan and Gary Smith.

Catch up with our earlier DAC previews at these links:

DAC 2013 Preview I: Putting users first and marking 50 years

DAC 2013 Preview II: Panels

DAC 2013 Preview III: Embedded

DAC 2013 Preview IV: Management and Training Days

DAC 2013 Preview V: Rounding out the keynotes

The post DAC 2013 Preview VI: CEO ‘visions’ added appeared first on Tech Design Forum.

ARM-based mobile processor shipments continue to provide more than half of the total shipments, but that share has fallen from 64 per cent in 3Q09, when ARM started to break out shipment numbers to 52 per cent in 1Q13. In 3Q12, the share had dropped to 50 per cent. The strong seasonal dependence of mobile phone shipments means the proportion of ARM’s sales into the sector climbs strongly in the fourth and first quarters of the year after a third-quarter slowdown or dip.

However, as annual mobile-chip shipments now exceed 60 per cent of the global population, they could easily plateau in a few years if they are not close to that point already – roughly 4.5 billion mobile chips were shipped in both 2011 and 2012, following a growth of more than 20 per cent over 2010.

In his keynote speech at CDNLive EMEA 2013, ARM embedded-processors vice president Keith Clarke, said: “Eight point seven billion chips shipped in 2012 with ARM processors inside. Of those, 2.2 billion were embedded processors. That number doubled in two years and more than doubled over the previous two years. We see that growth continuing.”

ARM is pinning a lot of its hopes on the Internet of Things or, as Clarke said the company prefers: “connected intelligence”. He argued that in a world where green concerns are coming to the fore, “connected intelligence is critical”.

“We will connect the previously unconnected. Even to something as simple as the street lamp you can add connected intelligence, and make the street lamp more efficient by only turning it on when it needs to,” Clarke said. “Every device will need some sort of connection.”

Clarke said one aspect of that is a collaboration with cellular service provider Vodafone. “We are looking to build a platform for machine-to-machine communications to give you quick access to a working system.”

Clarke also pointed to ARM’s role in white-space radio: “There is an opportunity here for a bit of innovation. The Weightless Special Interest Group has some special technology here. It supports a range of up to 10km with the low power you get with Bluetooth with very low-cost silicon. And it was designed for machine-to-machine communications.”

At the other end of the scale, ARM is working with Cadence to bring engineers with limited experience of microprocessor-based control into the 32bit world. He described a tool built on top of Verilog-AMS. “It is for designers who are very familiar with analog but less familiar with digital. They want to upgrade from a 8051 or similar microcontroller to something more capable. Very often, they are going to a Cortex-M0. We have put together this example system that shows you how you can simulate analog with digital in the same environment,” said Clarke.

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