After all, a lot of its raw components look familiar. Incisive and Palladium XP are recognized verification environments. Both the Virtual System Platform and the Rapid Prototyping Platform have also now been around for a while.

But the important thing here is the combination of acceleration (there’s both in-circuit acceleration and more accelerated VIP in the new package) and integration across the SDS’ components.

So, where once upon a time you needed separately maintained environments for in-circuit emulation and RTL simulation, the SDS allows you to work with just one. Indeed, the idea is to bring some uniformity through the chain across virtual prototyping, RTL simulation, acceleration, emulation, and FPGA-based prototyping.

VIP is also becoming one of this year’s battlegrounds. The Cadence Accelerated VIP catalog has been tailored for compatibility across the SDS and now includes a clutch of the most common interface standards: ARM’s AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.

Faster and more efficient, up to 10X, Cadence claimed this week. “A single heterogeneous environment for system-level verification.”

We’ll be going into more detail the suite early next week. Stay tuned.

A lot of responses from analog designers are that he should get his group to spend more time on getting Spice to run faster. At the same time as recommending that analog engineers start to consider crossing the Rubicon into the world of digital simulation, Beckley wanted to reassure the engineers who just want a faster Spice that a faster Spice is indeed on the way.

“We are working feverishly on a next-generation fast Spice,” Beckley claimed, that will probably start to see a rollout in the second half of the year.

The problem with many designs that need Spice simulation is simply that they are too big. Beckley said analog engineers should consider “real-number modelling rather than going to Spice” to simulate some mixed-signal designs, particularly those of the big-D/little-A variety.

“Real-number modelling has been around for a long time in the digital languages,” Beckley explained. “And it opens up the option of using assertions for mixed-signal simulation. But it has languished for the most part.”

It has taken off a little in the past couple of years, Beckley claimed, describing work at Texas Instruments to use it. “The results are stunning: a 300 times improvement in performance if you can move out of Spice and into real-number modelling and event-driven analysis.”

No-one is going to model an RF amplifier using the real-value support of a digital simulator but, as a 2009 white paper from Cadence pointed out, the accuracy of a discrete, real number-based model is probably enough to satisfy a pin-connectivity test that might need a large number of simulation cycles to test the various events and states that the target chip may face.

Learning the digital tools is not the only problem. “A lot of you work in the Virtuoso cockpit,” he conceded. So, the company is working to bring greater support for the digital tools into Virtuoso itself so that it is easier to compare results from different simulation modes and control verification runs that use the digital tools. Some of this work is already ready, such as the amsDMV tool developed by Cadence’s operation in Livingston, Scotland.

“Cadence has brought a lot of digital functionality to your analog cockpit,” said Beckley.

Beckley said the key to the upcoming fast Spice tool lies in a number of senior engineers who joined Cadence recently – namely four of the team that formed Nassda. He said the next-generation fast Spice engine and the tools around it represent “a big focus area for us”.

One notable feature was that, although Intel is careful not to use the word ‘fin’ in combination with ‘FET’, the profile of the channel is not unlike that of a fin in the natural world – tapering as it nears the top. It raised the question: is this what Intel wanted or is what is possible using current manufacturing techniques?

Gold Standard Simulations, a startup specialising in nanometre-scale simulation that has formed out work in Professor Asen Asenov’s group at the University of Glasgow, has released results of simulations that tend to point to the latter. You probably don’t really want a fin shaped like this but, if that’s what you have, it will work, just not as well as you would like.

The problem with the tapered fin, according to GSS, is that it tends to force carriers to the narrowest part at the top at higher voltages. This leads to a very high, focused current density, which may affect long-term reliability.

The taper also changes the dependence of threshold voltage on gate length as the current at low voltages moves down the fin towards the heavily doped region designed to stop carriers moving into the bulk silicon. As the fin thickens, the gate begins to lose its control, with the result that the tapered fin is not quite so good on short-channel effects as the ideal rectangular fin. That is probably not great news for Intel as it tries to move into mobile devices but, if these fins have the same overall performance as the graphs shown last year of the trigate versus regular CMOS, it should give the chip giant a sizeable advantage in low-power performance.

VERIFICATION

Guides

• Assertion-based verification: ABV claims ever greater adoption but is it being thoroughly implemented? These foundations will help you build an effective methodology.

• Verification IP: Proliferating I/O, memory standards and more are making VIP one of 2012’s liveliest markets, particularly as competition between Synopsys and Cadence intensifies.

Technical article

• Using assertions in ‘elemental analysis’ for airborne hardware development – Part Two: The concluding installment describes the use of assertion-based verification to meet ‘elemental analysis’ and robustness testing for major aviation projects. Newcomers will find Part One here.

EMULATION

Technical article

• Emulation delivers energy efficiencies and economies of scale: The technique’s benefits include more than just speed and visibility. It even has its ‘green’ side.

Blogs

• Mentor boosts Veloce emulator: A new chip doubles the emulator’s capacity while a software update addresses historical limitations.

• No more spaghetti: Guest columnist Richard Pugh on how virtual lab environments can help you to leverage traditional emulation tasks more efficiently.

PROTOTYPING

Guide

• FPGA prototyping: A hot topic because of the needs to cut time-to-market, manage the complexity of final silicon, and foster hardware/software co-design. But how do you chart the best course?

Technical article

• What can FPGA-based prototyping do for you? A sample chapter from the Synopsys/Xilinx-authored FPGA-based Prototyping Methodology Manual goes deeper into the different strategies available, with valuable reference to real-world case studies.

Blogs

• Xilinx revamps tool suite: The new Vivado software is architected for designs at 30nm and below.

• Synopsys updates Synplify: New release of the popular FPGA synthesis suite boosts efficiency and eases prototyping.

• Blue Pearl tightens integration to Synplify: Timing analysis constraints smooth the synthesis task.

NOW ONLINE

• Guide: FinFETs

• Guide: Fully depleted silicon-on-insulator

• PCB: Overcoming increasing complexity with automation

• Event: New England User2User stresses board-level and verification issues

• Newsletters: Issue #3: Highlights from DATE 2012 and more

The conference has four strands – PCB Flow, High-Speed, PADS and Functional Verification. Alongside the Mentor presenters, users offering papers include Alcatel-Lucent, AMD, Avid Technology, General Dynamics, Harris and Raytheon.

Some of the papers were also given at last month’s Silicon Valley U2U, and one or two caught out attention generally.

Chuck Ohrbom, an electrical engineer with ViaSat will discuss constraints-driven design. His abstract reads:

“The presentation will focus on a comprehensive use of the DxDesigner/Expedition flow toolset which allows for rapid implementation of printed-wiring-assemblies. Central to this method are the DxDesigner schematic capture tool, the CES constraints tool, and the Auto-router feature of the Expedition layout tool. Stylistic methods will be presented which lend to ease-of-understanding and design re-use. Also best-practices within the design flow will be covered.”

Ohrbom will be going a little further than just presenting by also setting out “a real-time challenge design” to be addressed with  audience participation.

In the Functional Verification strand, Pedram Riahi, a senior staffer at Raytheon, will review the potential in the Accellera-backed Open Verification Methodology (OVM) for use on FPGA designs. His abstract states:

“In any company, there is always a challenge to adopt a new tool (i.e., a new language or a new methodology) for both individuals and teams, specially if the last tool has been in the toolbox for not years, but decades. Adopting SystemVerilog to replace VHDL, and introducing OVM as an advanced functional verification tool to the decades-old FPGA Design process, which has never had a place for it, are not exceptions either. This presentation will discuss how this adaptation took place, how some of the challenges were overcome and how some of them are being dealt with currently.”

Certainly, there’s a large audience out there for some practical insights into OVM as it gathers more and more momentum.

Finally in our preview, the day opens with a keynote on “Creating Measurable Value Through Differentiation”, from Mentor’s Don Kurelich. It’s a version of the excellent address CEO Wally Rhines gave at the Silicon Valley edition and well worth getting up early for.

Attendance at U2U is free-of-charge, and the event runs from 8am – 4pm with the full program downloadable in PDF format here. Mentor has also made arrangements for attendees to receive free parking on the Bentley campus.

I’ve been thinking about my 6.5 years at Mentor’s emulation division, and looking back, I have seen tremendous changes in many things; customers, products, and verification methods — but probably the biggest change I notice is the sheer scale in our portfolio of emulation solutions we now offer. Back in 2005, we had a handful of them, whereas now we offer around fifty, covering applications such as video/audio, networking, wireless, storage, memories, CPUs, and bus protocol standards.

An Italian colleague calls them “solution tomatoes”, because our customers use them with emulation in the same way tomatoes are used in Italian cooking — everywhere! That demands a big effort from us, not just to maintain support for existing protocol standards, but also to keep an eye out for the emerging standards our leading-edge emulation customers need for the verification of their complex SoCs.

About a year ago, we started a new area — virtual solutions. For years, customers have craved a software solution with the same functionality as in-circuit emulation (ICE) hardware applications, but without the hardware itself — since the latter is troublesome to set up, limits the flexibility of deployment across multiple teams, and can require a lot of management, especially in cabling to the emulator. A few years ago I visited a customer’s lab and was amazed by the setup required for the dozens of hardware solutions they had connected to our Veloce emulator. I was reminded of a TV ad I saw years ago with Monty Python’s John Cleese, who was promoting a new hi-fi/TV system, saying the benefits were that “you don’t have a plateful of spaghetti hanging out the back.” How true. It’s a pity we couldn’t offer a software version back then for those customers.

So the virtual lab idea was born, with software-only solutions providing the same functionality as traditional ICE products. These are now coming on-line at Mentor for important applications such as video/audio, networking, bus protocols, and so on. We named these liberating technologies VirtuaLAB. It satisfies our customers’ requests for a virtual lab to conduct their verification, using large, server-based Veloce emulators to deliver massive numbers of verification cycles from a remote center. Users can sit at their desks and perform all the required setup, control, test, debug, and analysis tasks without ever having to touch any hardware.

VirtuaLAB is a tremendous step forward. It delivers an environment that is less error-prone during setup and reproducible and shareable across verification teams and multiple applications. So, thanks to this innovation, verification of multi-chip standards has come a long way in 6.5 years — and there’s no more spaghetti hanging out the back of the emulator.

Even before its formal launch, Veloce2 is apparently doing well. Eric Selosse, vice president and general manager of Mentor’s emulation division, said it has sold more units in the pre-launch, beta-testing phase than its predecessor did in its lifetime. There are some Veloce I chips left but with no plans to make more of those on its old process technology, it has almost sold out.

“We have invested very significantly in the front-end software that allows us to prepare the design for the emulator,” said Selosse, combining that with the custom ASIC to bring down compile times.

“We are not using a commercial FPGA from Altera or Xilinx,” Selosse added. “By using our own ASIC, we have been able to significantly reduce compile times. FPGAs have different goals to emulators. The goal of the FPGA is to maximize the number of logic cells used. We made a clear architectural decision to optimize for routability. As a result, if an engineer makes a modification to the design, they can quickly get a new model compiled for the emulator. That process might take hours for an FPGA; it’s five minutes for Veloce.”

The new chip for Veloce II is based on a 65nm process, offering higher density than its predecessor but without the much higher development cost of a device aimed at a sub-30nm process.

Another change that Mentor has made is to help with globally distributed design. “The emulator is becoming a shared resource,” said Selosse.

Sitting in a data center, accessible to developers around the world, it becomes tricky to patch the peripherals for an in-circuit emulator to support different projects. So, the company has developed software modules that allow blade servers to be used as virtual peripherals that are switched in and out dynamically. The VirtuaLab modules use the standard SCE-MII protocol to communicate with the emulator.

To reduce the number of cycles that are ‘wasted’ by booting software on the virtual hardware, it is possible to store snapshots of the state of the emulator at any point and restore that at the start of a session. As a result, software testing can resume from a known point without having to wait for several hours for the boot sequence to complete – something that would otherwise be run many, many times.

The snapshots also make it possible for software developers to replay the sequence of events leading up to the expression of a bug, allowing the actual hardware to be used on another project or a new verification run.

Introducing the Vivado software, Tom Feist, senior marketing director for design methodology at Xilinx, said: “Four years ago we said we needed to invest in a next-generation design suite. Our current suite, ISE, is about 15 years old. But times have changed. The FPGAs and programmable devices have become much more complex. Xilinx has moved from being just a programmable-logic vendor to what we call ‘all programmable’.”

Feist said the company sees IP reuse as crucial to cut the time it takes to put multi-million gate FPGA designs into production, something of which ASIC designers are only too aware. However, the plan is to move at least some of the IP reuse on the system level. “We are focusing not just on RTL but algorithmic-level design,” said Feist.

It’s not in the standard version of the suite, but Xilinx is using its acquisition of AutoESL to provide synthesis from the algorithmic level. The other strand to Xilinx’s plans for IP reuse are centered on IP-Xact. “It doesn’t provide a lot for the end user directly but it does help automate flows,” said Feist.

As well as being used to package the Xilinx-supplied IP cores, the IP-Xact tools can be used to take parameterizable customer-defined cores and package them as well. “We use the IP-Xact metadata to define the interfaces so that the blocks can be stitched together using just one line of code,” Feist explained.

IP synthesized from the algorithmic level is also put through the packaging system. “It automatically performs interface synthesis so you can stitch the blocks together very rapidly,” said Feist.

Similar to the change in ASIC synthesis towards physically aware synthesis, Xilinx has rewritten its core implementation tools to focus on the problems of wire length and congestion. The company has found that, even with the buffered array structure of an FPGA, long wires are troublesome and tend to increase congestion. So the company has moved away from good old simulated annealing to an architecture that allows more efficient handling of placement.

Also like the ASIC flows in place now, Xilinx has adopted a standard database format. But it is one of Xilinx’s own design rather than a standard such as Open Access. “We used standards where we could. We support Synopsys design constraints [SDC] and Tcl. But the data model had to be optimized for our needs. In the ASIC world, everything is fine-grained. But the FPGA is a coarse-grained architecture.”

The company looked at obtaining an OEM version of a mixed-language simulator to support designs that use SystemVerilog and VHDL code but opted to implement its own. “We looked externally but none of the suppliers wanted to do it,” said Feist.

Dave Reed, senior director of marketing at SpringSoft, said the core of the new Laker custom and analog design tool is a focus on analog prototyping: taking schematics and using automated layout techniques to gauge how well a design is going to work. This, he said, is driven by the way proximity effects come into play in sub-50nm nodes. How close a transistor lies to the edge of a well or to another device can significantly change key parameters such as threshold voltage and transconductance. So, topologies that work well in one process and, indeed, on another part of the chip, may not work so well in a new location.

“At the schematic level, I have no idea if an element will be close to the edge of a well. So you can use layout exploration to get an idea of how the circuit will behave,” said Reed.

The problem is getting even a prototype of a layout done quickly. If you have a constraint-driven flow, you can use rules to determine how placements are driven by considerations such as proximity to a well boundary. “The key problem is how do you generate the constraints in the first place that tell the tool what to do? Customers have not wanted to spend a lot of time in defining constraints. So we have been working on a way to define them automatically.”

The latest release of the tool contains code that attempts to identify common subcircuits such as voltage references, cascode pairs and current mirrors. “There are 20-plus structures that we have taught it,” said Reed, adding that it will recognize logic structures such as NOR gates as well.

Some of the panelists at DATE talked about the tedium of dealing with common subcircuit elements such as these and how they detract from the effort needed for new elements that need the attention of an expert circuit designer. Something that automates the placement of subcircuits that offer little scope for differentiation may be what is needed for constraint-driven design to become accepted.

The move beyond 30nm has called for further changes in Laker. Mark Milligan, vice president of corporate marketing, said: “We have created a new DRC engine that is capable of understanding 20nm rules. You have to push the understanding of the design rules into the design process.”

The new DRC engine is not meant to replace the live link that the company built to Mentor Graphics’ Calibre – an external DRC tool remains the preferred route for sign-off level checks. The internal engine is meant to guide the designer as to what makes sense in a custom layout or cell design. Although design rules are far more restrictive than ever, the element that has pushed the need for constant design-rule analysis is double patterning.

Because the separation into masks is a graph colouring problem, and you generally only have two colours to play with, knowing whether a given juxtaposition of features is viable is essential.

“We color as a way of checking whether the final coloring is possible,” says Reed, adding that although there is still a debate over whether coloring will be done by custom and cell designers or handled automatically by tools, the trend seems to be towards putting that control in their hands. ” We have to make sure that the colouring is possible.”

Having embraced the Open Access database in recent releases of its tools, SpringSoft has made some changes to improve speed.

Reed explained: “Although the CPUs themselves have been getting faster, there has been a comparative slowdown related to disk I/O. There is less local storage: more of it is off in a computer room somewhere. We looked at how we could minimize disk accesses. the part of the Open Access database that talks to files is a plug-in — you are allowed to rewrite. So we did and achieved a two to ten times speed-up,” said Reed.

The difference is experienced when reading and writing designs out from the in-memory database but also during tool operations. “We found that with some things Open Access was going to disk when it didn’t need to. Even redrawing the screen involved a number of disk accesses,” Reed added.

Right now, Rhines picked out five areas in his U2U keynote.

1. Low power design at higher levels. Mentor already has Vista for doing this at the architectural level, but in future, Rhines wants to increasingly leverage his company’s presence in embedded software to build a bridge between hardware and software decisions on power. In particular, he sees Mentor’s push on open source embedded development, particularly through its Sourcery Code Bench suite, as a way of enabling the software team to look at how its code affects power dissipation in a familiar environment.
2. Functional verification beyond RTL simulation. Rhines noted that the Accellera-backed Universal Verification Methodology (UVM) is set to grow by 286% in the next 12 months – a healthy looking number, but remember we are still in the first stages of its adoption. Mentor specifically is rolling out what it calls ‘graph-based verification’, the goal there being to use analysis to elminate simulation redundancy – “Most stimulus is restimulating what’s already been simulated” – and to drive more intelligent test. One advantage of these techniques, Rhines added, is that they can be scaled linearly by adding CPUs to boost productivity. This could be particularly important in a third area, simulation, where today’s high costs could be mitigated with moves to cloud-based multi-user access.
3. Physical verification beyond DFM. Much of this may be for the longer term future, particularly where it applies to 3D chip stacking, but already technologies such as programmable electrical rule checking are adding more to the post DRC/DFM arsenal. 3D will also bring with it a greater emphasis on overstressing and ESD.
4. DFT beyond compression. Again 3D IC test is going to be an issue… eventually (Rhines takes a realistic view that widespread implementations are still some way off, despite hype around the technology). However, there is already scope for moving towards more reuse within advanced hierarchical test methodologies.
5. System design beyond PCBs. A particularly interesting one, since PCB is one of the most mature markets (overall, it’s hardly grown significantly in 20 years, though remains an important volume area for Mentor), but Rhines argued that Mentor – particularly after its acquisition of Valor – can now offer much richer dataflows and more abstracted views. Then, there are also the challenges posed by packaging, burgeoning interconnects and, again, the impact of 3D.

It’s an interesting list, a mixture of technologies that are in many cases available now, but have yet to move beyond the power user market (or are only just beginning to) as well as others that will require some innovation. We got a chance to sit down and go through some of these ideas in more detail with Wally at U2U, so consider this some high-level trendspotting and food for thought before we post the full interview next week.

Meanwhile, given that multi-disciplinary design is a hot topic right now, the keynote added a sixth “And even beyond…” theme, reflecting areas beyond electronic design where Mentor is getting some pull. These include potentially huge opportunities such as thermal management and the design of electrical systems in vehicles, aerospace and a host of other markets.

Perhaps a more limited, but just one of those very cool examples though, is that Ping has been using Mentor simulation technology to design a better golf club. What’s the opposite of a Mulligan?