The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]

The article reviews the design assessment process that a company should undertake when developing an analog-centric application-specific integrated circuit (ASIC). The authors argue that a number of myths surround strategies that incorporate a large amount of specialist analog design work, including evaluations related to cost and functionality. In particular, the need for differentiation in today's [...]

Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL [...]

A team from RFMD describes a design upgrade for one of the company’s devices, the ML5800 transceiver. The chip is used in cordless telephones and has sold more than 20 million units. Because of constraints upon the different portions of the project and a wish to maximize reuse from the earlier chip, the company developed [...]

Process design kit (PDK) standards are one area that could greatly help reduce the disproportionate time and effort required to realize the analog portion of a design. PDKs have existed for two decades and provide access to foundry-verified data files for such AMS design elements as parameterized layout cells (PCells). However, most have been constructed [...]

The paper presents a fully parallel transistor-level full-chip circuit simulation tool with SPICE accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple nonlinear subdomains based on circuit nonlinearity and connectivity. A parallel iterative matrix solver is used to solve the linear domain while nonlinear [...]

Circuit noise problems can originate from a variety of sources. By carefully examining attributes of the offending noise you can identify it’s source, thereby making noise reduction solutions become more apparent. There are three subcategories of noise problems: device, conducted and radiated noise. If an active or passive device is the major noise contributor, you [...]

As the market continues to push for higher performance at lower cost, trusted personal devices (TPDs) must also be able to exchange greater volumes of data, voice or streaming video at ever higher bit rates, while transmitting and receiving securely under multiple telecommunication standards. Reductions in cost and time-to-market can only be achieved by integrating [...]

The article describes an algorithm that combines performance and variation objectives in a behavioral model for a given analog circuit topology and process. The tradeoffs between performance and yield are analyzed using a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a signi?cant improvement in overall simulation time and ef? ciency compared to [...]

The 802.11 family of wireless local area network (WLAN) standards is becoming ubiquitous. Products for its various fl avors – up to and including its latest 802.11n incarnation – must reach the market as quickly as possible. This implies a need for rapid prototyping, typically on an FPGA platform. This article describes how the design [...]