EDA
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Blindsided by a glitch
Logic glitches in asynchronous clock domain crossing paths can arise even when synthesis tools declare a design’s RTL and gate-level [...]
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RTL debug: integrating automation and vizualization
Root-cause analysis of detected errors is a key design step. Debugging can take more than half of the verification effort. [...]
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Three essential steps to SoC design and verification
An evolved ESL-to-RTL methodology flow addresses the ‘discipline gaps’ between software and hardware engineering by using three system level-based software-hardware [...]
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DRC+: a pattern-based approach to physical verification
DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to [...]
Design to Silicon
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Tested Component to System
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Verified RTL to gates
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