verification

August 11, 2017

Keynotes announced for DVCon Europe

DVCon Europe 2017 has announced two keynote speakers for the conference to be held in Munich, Germany in mid-October.
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June 15, 2017

Early access view of portable-stimulus standard released

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.
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June 15, 2017

DAC 2017 preview: Breker

At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.
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April 28, 2017

ARM deploys data-center tech to study verification patterns

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
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March 8, 2017

Verification Futures tackles safety and security

The Verification Futures conference organized by European EDA consultancy TV&S returns for its seventh year in early April with a focus on safety and security in the growing area of cyber-physical systems.
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December 7, 2016

Overcoming electromigration analysis limitations for larger on-die power grids

Award-winning paper describes new strategy offering both greater speed and accuracy.
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October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
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October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
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September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
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May 25, 2016

Register tools appear ahead of DAC

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
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