verification

March 8, 2017

Verification Futures tackles safety and security

The Verification Futures conference organized by European EDA consultancy TV&S returns for its seventh year in early April with a focus on safety and security in the growing area of cyber-physical systems.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
December 7, 2016

Overcoming electromigration analysis limitations for larger on-die power grids

Award-winning paper describes new strategy offering both greater speed and accuracy.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: , ,
October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , ,   |  Organizations:
October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
May 25, 2016

Register tools appear ahead of DAC

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
December 18, 2015

Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
November 16, 2015

Cadence shifts emulation to the data center

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
October 8, 2015

Expanding role of UVM takes center stage at DVCon Europe

Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.

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