The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.
Formal, AI and UVM form key parts of the OneSpin agenda for this year's Design Automation Conference.
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.
But the bridge standard's European backers still need greater support from the big EDA vendors.
Tech Design Forum talked to the general and program chairs of DVCon Europe about the conference and how it seeks to show the expansion of IC verification methodologies to the system level.
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