UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.
The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
Focus on systemic issues matches DVCon Europe event to European interests
Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
VCS AMS updates AMS verification tool and methodology
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Accellera has vendor extensions for IP-XACT that allow tool-specific metadata to be added to support activities such as power-aware verification and floorplanning.
Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
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