TSV


September 27, 2022

Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures

Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Article  |  Topics: EDA - DFT  |  Tags: , , , , , , , , , ,   |  Organizations:
January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
May 20, 2014

Vorsprung durch 3D technik for Audi

The automotive sector could become one of the key markets for 3D integration according to the head of Audi's progressive semiconductor program.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,
April 1, 2013

DAC 2013 Preview I: Putting users first and marking 50 years

In the first of our weekly DAC 2013 previews, we discuss program highlights with general chair Yervant Zorian, including an expanded Designer Track, keynotes and golden jubilee celebrations.
February 19, 2013

ISSCC 2013: Silicon and organic stacks for prosthesis

TSVs and layers of organic electronics provide two ways to build medical sensors and prosthetics, as shown at ISSCC 2013.
December 13, 2012

3D-IC integration prospects improving, say IEDM researchers

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
Article  |  Topics: Blog Topics, Conferences, Design to Silicon  |  Tags: , , , , , ,   |  Organizations: ,
June 14, 2012

Strained silicon beats TSV stress in 3DICs

Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
March 26, 2012

Synopsys builds 3D into tool portfolio

At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
March 22, 2012

TSMC Altera heterogeneous integration is cool but is it 3D?

This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
Article  |  Topics: Commentary, Design to Silicon, Blog - EDA, PCB  |  Tags: , ,

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