September 27, 2022
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
January 7, 2015
At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
May 20, 2014
The automotive sector could become one of the key markets for 3D integration according to the head of Audi's progressive semiconductor program.
April 1, 2013
In the first of our weekly DAC 2013 previews, we discuss program highlights with general chair Yervant Zorian, including an expanded Designer Track, keynotes and golden jubilee celebrations.
February 19, 2013
TSVs and layers of organic electronics provide two ways to build medical sensors and prosthetics, as shown at ISSCC 2013.
December 13, 2012
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
June 14, 2012
Texas Instruments had good news for teams that want to assemble 3DIC stacks using thru-silicon vias (TSVs). The stress induced by the copper TSVs is not as bad as many feared for nanometer-scale transistors.
March 26, 2012
At the SNUG event this week, Synopsys is taking the wraps off its plans to support 3DIC, with updates to tools for physical design and verification.
March 22, 2012
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance