timing analysis


June 7, 2016

Analyzer merges constraints for multiple timing modes

Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
March 5, 2014

Visual timing tool focuses on high-speed PCB signals

Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
Article  |  Topics: Blog - PCB  |  Tags: , , ,   |  Organizations:

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