SystemVerilog

February 1, 2018

Metrics introduces elastic compute to handle peak-time verification

Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
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June 15, 2017

Smart code editor adds SystemVerilog support

Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking
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June 9, 2017

DAC 2017 preview: Verific Design Automation

Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
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May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
September 2, 2015

Early registration opens for DVCon Europe 2015

Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
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April 22, 2015

Thursday returns as DAC training day

The Design Automation Conference in San Francisco this year will again feature a day of half-day training courses provided by Doulos on Thursday, June 11 .
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February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
November 18, 2014

Startup builds environment for custom EDA tools

Canadian startup Invionics has launched a development environment and packager intended to make it easier for users within chipmakers and design houses to build customized tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
Article  |  Topics: Product, RTL, Verification  |  Tags: , , , , ,   |  Organizations:

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