SystemVerilog

December 28, 2018

Why Mentor backs the PSS-DSL input format for the Portable Stimulus Specification

With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,
July 5, 2018

Cloud makes hardware acceleration more accessible

After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.
June 18, 2018

DAC 2018 preview: Verific

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
February 1, 2018

Metrics introduces elastic compute to handle peak-time verification

Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
June 15, 2017

Smart code editor adds SystemVerilog support

Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking
Article  |  Topics: Blog - EDA  |  Tags: , , ,
June 9, 2017

DAC 2017 preview: Verific Design Automation

Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
September 2, 2015

Early registration opens for DVCon Europe 2015

Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
April 22, 2015

Thursday returns as DAC training day

The Design Automation Conference in San Francisco this year will again feature a day of half-day training courses provided by Doulos on Thursday, June 11 .
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

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