SystemVerilog

March 4, 2024

Latest version of Verilog-AMS ready for release

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
February 8, 2024

Accellera forms working group for mixed-signal interfaces

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
April 17, 2023

Achieving functional coverage of multi-language designs

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
July 7, 2022

DAC 2022 preview: Verific Design Automation

The tool development specialist will demonstrate its broad portfolio at next week's Design Automation Conference in San Francisco.
Article  |  Topics: Blog - EDA, - Tool development  |  Tags: , , , ,   |  Organizations: ,
April 29, 2022

Navigate variables and lifetimes in SystemVerilog

Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations: ,
December 3, 2021

DAC 2021 preview: Verific

Tool development enabler Verific will demonstrate its parsers, including a combination with the INVIO API platform at DAC 2021 in San Francisco next week.
Article  |  Topics: Conferences, Tool development, Verification  |  Tags: , , , , , , ,   |  Organizations: ,
December 11, 2020

OSVVM updates go into Riviera-Pro

Aldec updates tools to add support for the latest release of the VHDL verification methodology.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Article  |  Topics: Verification  |  Tags: , , , ,   |  Organizations: , ,
July 1, 2020

Sigasi creates SDK for custom editors

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,

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