system-in-package


June 1, 2023

Does 2.5DIC call for IC design tools for the packaging?

Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
November 23, 2022

Chipletz pushes packaging design for AI, HPC and immersive use-cases

The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
November 8, 2021

Chiplets may have to prove themselves for secure operation

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations:
December 21, 2020

Plasmonics may point way to faster interchip comms

Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations: ,
April 4, 2019

ODSA weighs options for chiplet interconnect

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
June 27, 2018

EDA needs to work on the back end, says Qualcomm

It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
April 24, 2015

Do you need more stress (analysis) in your life?

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
March 10, 2015

Douglas Adams 1: Apple Watch 0 (game in progress)

'Bling' for fashionistas and the B Ark lot. Apple Watch limps as the S1 SIP fails to offer convincing battery life. Silicon shortfall still dogs wearables.
Article  |  Topics: Blog Topics, Commentary, General  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors