synthesis


November 27, 2018

Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results

Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
Article  |  Topics: Blog - EDA, - Product  |  Tags: , ,
June 16, 2017

DAC 2017 preview: Plunify

Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
February 7, 2014

Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%

Uses improved logic optimisations and a new approach to meeting timing.
Article  |  Topics: Blog Topics, Product  |  Tags: , , , ,   |  Organizations:
April 24, 2012

Xilinx revamps design software for new processes

Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , ,   |  Organizations:
March 15, 2012

DATE notebook: Constraints smooth path for FPGA synthesis

Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.
March 15, 2012

CDN Live: Cadence’s Encounter revamp collates innovation

Performance boost claimed from streamlining optimization across synthesis and layout using modeling, novel CTS strategy and 20nm-ready features.

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