simulation

May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
February 12, 2018

DVCon US 2018 preview: Mentor

The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , , ,   |  Organizations: , , ,
March 2, 2017

How formal concentrates ISO 26262 fault analysis

Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.
February 27, 2017

Cadence tunes up simulators and FPGA prototyping

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
January 10, 2017

Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation

Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
Article  |  Topics: ESL/SystemC, Product  |  Tags: , ,   |  Organizations:
August 24, 2016

Cadence building photonics environment around Virtuoso

Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , ,   |  Organizations:
April 4, 2016

HyperLynx made broader and easier to use

HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
November 16, 2015

Cadence shifts emulation to the data center

Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
October 19, 2015

Mentor targets next-gen Ethernet with emulation

Vendor adds verification support for 25G, 50G and 100G Ethernet through emulator-based virtualization.
Article  |  Topics: Blog - EDA, Embedded, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,

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