SDC


June 7, 2016

Analyzer merges constraints for multiple timing modes

Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
April 24, 2012

Xilinx revamps design software for new processes

Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , ,   |  Organizations:
March 15, 2012

DATE notebook: Constraints smooth path for FPGA synthesis

Blue Pearl Software has extended its reach into the world of field-programmable gate array (FPGA) design and verification with a project that has culminated in a tighter integration between its timing analysis tools and the Synopsys Synplify Pro tool.

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