Bridging the gap between IP development and qualification for P&R
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
RTL analysis
Synopsys to acquire Atrenta
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
Synopsys claims latest Design Compiler shrinks existing netlist area, leakage up to 10%
Uses improved logic optimisations and a new approach to meeting timing.
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