RISC-V

November 3, 2023

Codasip pips Arm to commercial CHERI with RISC-V version

Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.
October 31, 2023

Imperas builds model of Tenstorrent AI core

Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
July 25, 2023

Verification Futures heads to the US in September

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
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June 1, 2023

Semidynamics adds flexible vectors to RISC-V cores

Semidynamics has released a customizable vector unit with out-of-order execution support to accompany its 64bit RISC-V processor cores.
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April 17, 2023

Semidynamics pushes configurability on RISC-V core for HPC

Processor IP company will incorporate custom instructions and other changes in its superscalar core, which includes a novel memory unit for sparse matrices.
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February 28, 2023

Imperas and Synopsys team on RISC-V debug

Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
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December 12, 2022

RISC-V gets verification and security IP additions

Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
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August 31, 2022

Intel and partners join for RISC-V development push

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
July 14, 2022

‘Shocking’ quality sees vendors organize around RISC-V verification

Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.

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