Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
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