January 2, 2018

Watch out for layout effects on finFET reliability

As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.
Article  |  Topics: Blog - EDA  |  Tags: , , ,
August 30, 2016

Design trade-offs in using DDR4 memory for enterprise applications

A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
May 5, 2016

Functional safety and high reliability for FPGA designs – eight videos show you how

Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
Article  |  Topics: Blog - EDA, Embedded, - General  |  Tags: , , , , , ,   |  Organizations:


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors