April 6, 2017
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
June 9, 2016
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
June 7, 2016
A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
June 7, 2016
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
March 9, 2016
Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
October 9, 2015
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
October 6, 2015
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
September 29, 2015
Stability is the watchword as AMS and MEMS specialist Tanner retains much of its independence - a 'start-up with a billion-dollar company behind us'.
March 10, 2015
Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
November 4, 2014
Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.