place and route

June 16, 2017

DAC 2017 preview: Plunify

Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
April 6, 2017

Bridging the gap between IP development and qualification for P&R

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
June 7, 2016

ARM accelerates POP deployment for Cortex-A73

A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
June 7, 2016

Analyzer merges constraints for multiple timing modes

Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
October 9, 2015

IMEC 5nm test chip to explore EUV and SAQP litho options

IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
October 6, 2015

Samsung taps Mentor tools for higher yielding close-loop DFM

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
September 29, 2015

Tanner EDA @ Mentor Graphics: Steady as she goes

Stability is the watchword as AMS and MEMS specialist Tanner retains much of its independence - a 'start-up with a billion-dollar company behind us'.
Article  |  Topics: Digital/analog implementation, Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors