place and route

July 3, 2018

Fusion improves timing say Synopsys users

Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
June 22, 2018

GlobalFoundries plays with metal gear in search for solid gains

At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 19, 2018

Mentor targets DRC efficiencies for place-and-route with Calibre RealTime Digital

Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations:
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
June 16, 2017

DAC 2017 preview: Plunify

Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
April 6, 2017

Bridging the gap between IP development and qualification for P&R

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
June 7, 2016

ARM accelerates POP deployment for Cortex-A73

A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
June 7, 2016

Analyzer merges constraints for multiple timing modes

Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.

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