Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
Plunify will demonstrate its new Kabuto tool that recommends RTL fixes for FPGA designs at the Design Automation Conference.
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
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