multi patterning

February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 13, 2017

SPIE Advanced Lithography preview: Mentor Graphics

The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
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December 11, 2015

IEDM keynote: cost scaling will swap architectural changes for area

According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
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July 9, 2015

IBM and friends at 7nm: breakthrough or science project?

IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
June 18, 2015

The road to 7nm sees patterning multiply

Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
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November 4, 2014

From Darwin to Mao: how multi-patterning could move up the flow

Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
June 13, 2014

Path to 5nm plotted at DAC panel

Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound
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