mixed-signal design

March 20, 2017

Motion sensors get earache

Attacks using sound can upset accelerometers and make them produce false motion signals.
February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
September 14, 2016

Event: How ISO 26262 is driving automotive DFT requirements

Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:
June 6, 2016

ARM recruits design houses and tools for quicker IoT projects

ARM aims to recruit more startups to develop IoT SoCs around the Cortex-M0 with design-house network and easier access to EDA tools.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , ,
March 16, 2016

MEMS contest launches at DATE

The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: , ,
June 29, 2015

FastSpice update improves parallelism and adds wreal support

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
April 29, 2015

Automotive integration led by cabling concerns, says NXP

Cabling and its weight are helping to drive integration and a shift towards wireless communication within cars, says NXP's automotive CTO.
September 2, 2014

IoT mixed signal design: keep everything in the green

ARM and Cadence have teamed up to show how system-level and implementation-level representations of a mixed-signal design can be linked together and kept in sync as the project progresses.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , ,   |  Organizations: ,
June 10, 2014

Verilog-AMS release adds to power-aware analog modeling

Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:

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