MIPI


February 24, 2020

DVCon US 2020 preview: SmartDV

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.
Article  |  Topics: Blog - IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
February 27, 2018

Synopsys UFS 3.0 IP doubles bandwidth to flash

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
Article  |  Topics: Blog - IP, - Product  |  Tags: , ,   |  Organizations: , ,
October 17, 2017

Arm TechCon 2017 preview: Synopsys

Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
May 20, 2013

TVS expands VIP library

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
May 7, 2013

CDNLive EMEA: Cadence to buy Evatronix

Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
February 8, 2013

Cadence buys IP provider Cosmic

Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
February 27, 2012

Synopsys verification IP launch has bite

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

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