methodology


December 6, 2017

Learn how to simplify power states in UPF

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , ,   |  Organizations: , , ,
March 26, 2014

Better Software, Faster!: free virtual prototyping book available now

Free book explains virtual prototyping and includes case studies about virtual prototyping from Altera, Bosch, GM, Hitachi, Lauterbach, Linaro, Microsoft, Renesas, Ricoh, Siemens, and TI.
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations: , , , , , , , ,
February 25, 2013

DVCon: UPF and CPF harmony in low power is only a foundation

As DVCon begins, we interview Cadence's Qi Wang, who has led its efforts to converge the Common Power Format with its rival as the IEEE1801 standard is revamped.
Article  |  Topics: Blog Topics, Commentary, Conferences, Blog - EDA, - Standards  |  Tags: , , , ,   |  Organizations:
August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
June 11, 2012

Webinar on model-driven design for soft modems

Cognovo is running a webinar next week (19 June) on model-driven design for software-defined wireless modems.
Article  |  Topics: Blog Topics  |  Tags: , , ,
May 31, 2011

Cybersecurity goes back on the agenda.

A few weeks ago, the White House released its International Strategy for Cyberspace . To a technical audience, it’s a pretty thin document. But that’s fair enough – it’s intended for consumption by politicians, diplomats and policy wonks, not technologists. However, the strategy does make it pretty clear that the private sector has a big […]

Article  |  Topics: Blog - EDA, - General  |  Tags: , , ,

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