low power

June 3, 2014

Synopsys adds formal, CDC, low-power checks to Verification Compiler

Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Article  |  Topics: Product, Verification  |  Tags: , ,   |  Organizations:
March 26, 2014

Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation

Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , , ,   |  Organizations: ,
February 6, 2014

Cadence to buy Forte and build out HLS offering

EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
November 4, 2013

Rambus CEO calls for collaboration and an architectural focus for memory

Dr Ron Black also discussed his experiences with the Internet of Things in a lively keynote at the GSA Memory+ Conference in Taipei
Article  |  Topics: Commentary, Conferences, Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
October 24, 2013

Hybrid chip links ARM core with C-programmable deterministic peripherals

XMOS integrates xCORE configurable, deterministic multicore microcontroller technology with ultra-low-power ARM Cortex-M3 processor to create a low-power ‘programmable system on chip’.
Article  |  Topics: Blog - Embedded  |  Tags: , ,   |  Organizations: , , ,
October 9, 2013

Silicon Labs opts for security on M0+ low-power MCUs

Silicon Labs is aiming at Internet of Things applications with an ARM Cortex M0+-based MCU family with encryption engine and low-energy DAC for biasing analog circuitry.
Article  |  Topics: Blog - Embedded  |  Tags: , , , , ,   |  Organizations:
October 9, 2013

Jasper preps User Group and Architectural events

The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
Article  |  Topics: Blog Topics, Conferences  |  Tags: , , , ,   |  Organizations:
September 11, 2013

Intel tips 14nm processor, Quark core and SoC licensing plans

In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , ,   |  Organizations:
June 3, 2013

UPF group moves to consider system-power issues

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 22, 2013

DAC 2013 Preview VIII: Low-power design

Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.
Article  |  Topics: Blog - EDA  |  Tags: , ,

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors