Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Dr Ron Black also discussed his experiences with the Internet of Things in a lively keynote at the GSA Memory+ Conference in Taipei
XMOS integrates xCORE configurable, deterministic multicore microcontroller technology with ultra-low-power ARM Cortex-M3 processor to create a low-power ‘programmable system on chip’.
Silicon Labs is aiming at Internet of Things applications with an ARM Cortex M0+-based MCU family with encryption engine and low-energy DAC for biasing analog circuitry.
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
In a keynote at the Intel Developer Forum, CEO Brian Krzanich said the company would start making 14nm processors by the year end and confirmed intel would license SoC designs to be fabbed by other companies.
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.
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