Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.
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