low-power design

June 27, 2017

Sonics adds heat-aware DVFS to SoC power controller

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
March 7, 2017

POSTPONED: Get to grips with new PC, monitor energy regs

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Article  |  Topics: Blog - EDA, - Standards  |  Tags:   |  Organizations: , , , , , ,
February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
May 25, 2016

DAC 2016 preview: Mentor Graphics

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
June 23, 2015

Sonics updates tune memory and link width for speed and power

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 11, 2015

Two-day app challenge results in RTL power analyzer

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 8, 2015

CEA-Leti adds partners to FD-SOI low-power design centre

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , ,
June 8, 2015

Synopsys to acquire Atrenta

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
June 7, 2015

Docea adds API to model power software interactions

Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , ,   |  Organizations:

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