For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
EEMBC has released a benchmark and initial results that analyze peripheral performance on microcontrollers.
Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
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