Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.
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