low-power design

June 21, 2018

AI is all about low-energy hardware says Dally

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,
December 6, 2017

Learn how to simplify power states in UPF

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , ,   |  Organizations: , , ,
September 12, 2017

MCU benchmark homes in on peripheral power

EEMBC has released a benchmark and initial results that analyze peripheral performance on microcontrollers.
Article  |  Topics: Blog - Embedded  |  Tags: , , ,   |  Organizations: , ,
June 27, 2017

Sonics adds heat-aware DVFS to SoC power controller

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
March 7, 2017

POSTPONED: Get to grips with new PC, monitor energy regs

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Article  |  Topics: Blog - EDA, - Standards  |  Tags:   |  Organizations: , , , , , ,
February 21, 2017

Xilinx to bring analog conversion onto finFET FPGAs

Xilinx plans to add high-speed analog interfaces to its upcoming FPGAs to better support high-density 5G basestation designs.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , , ,   |  Organizations: ,
June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
May 25, 2016

DAC 2016 preview: Mentor Graphics

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
June 23, 2015

Sonics updates tune memory and link width for speed and power

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 11, 2015

Two-day app challenge results in RTL power analyzer

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:

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