IP

June 6, 2014

eSilicon to cut costs of ASIC development for IoT, other markets

Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Article  |  Topics: Design to Silicon, GDSII, Blog - IP  |  Tags: , , , ,
December 16, 2013

Synopsys puts physical IP prototypes into developers’ hands

Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations:
June 14, 2013

Synopsys launches single kit to optimize IP across PPA

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Article  |  Topics: Digital/analog implementation, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
May 7, 2013

CDNLive EMEA: Cadence to buy Evatronix

Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
March 11, 2013

Cadence to buy Tensilica

Cadence Design Systems has announced on the eve of CDNLive Silicon Valley that it has decided to buy configurable-processor company Tensilica for approximately $380m in cash.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
February 8, 2013

Cadence buys IP provider Cosmic

Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
December 11, 2012

FD-SOI vs finFETs mulled during IEDM

Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
Article  |  Topics: Blog Topics, Blog - EDA, - Industry Blogs, Tested Component to System, Verification  |  Tags: , ,   |  Organizations: ,
November 6, 2012

Companies go for patent protection in MIPS deal

ARM is among the companies aiming to avoid a patent portfolio falling into the wrong hands after the break up of MIPS Technologies.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: ,   |  Organizations:
November 6, 2012

Xmos in real-time protocol push with IP and hardware

Xmos is going back to its roots as a microprocessor architecture designed specifically for low-latency, real-time applications.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:

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