Breker adds automated system integration test generation for RISC-V
App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
IP
How to achieve faster, more relevant early-stage DRC with Recon
The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
ARM adds Cortex-A77 and Mali-G77 cores for 5G and ML
The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
DAC 2017 preview: Uniquify
Vendor concentrates on memory IP products at 2017 Design Automation Conference.
ARM TechCon: Mentor Graphics preview
Catch up with the vendor's plans for the ARM technical conference in Santa Clara later this month.
Cortus adds hardware floating point to low-area processor family
Cortus has added to its version 2 architecture a processor core that offers hardware support for floating-point code.
Mentor unites chip-to-package flow with Xpedition Package Integrator
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
Minimal 32bit IP cores tackle connected devices market
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
eSilicon to cut costs of ASIC development for IoT, other markets
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Synopsys puts physical IP prototypes into developers’ hands
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
PLATINUM SPONSORS
View All Sponsors