Vendor concentrates on memory IP products at 2017 Design Automation Conference.
Catch up with the vendor's plans for the ARM technical conference in Santa Clara later this month.
Cortus has added to its version 2 architecture a processor core that offers hardware support for floating-point code.
Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
Synopsys launches HAPS-DX, an FPGA-based IP and subsystem prototyping system, with an optimized toolchain and interoperability with HAPS-70 systems.
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
Cadence Design Systems has announced on the eve of CDNLive Silicon Valley that it has decided to buy configurable-processor company Tensilica for approximately $380m in cash.
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