Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
Ceva has developed its first processor architecture aimed squarely at deep learning.
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
EEMBC has turned its attention to heterogeneous computing with plans to create a new set of benchmarks.
IP supplier CEVA has made a development platform intended to speed up the prototyping of IoT and similar devices based on its TeakLite-4 DSP core.
Ceva has launched a software package intended to streamline the porting of convolutional neural network implementations to the XM4 DSP core.
Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
Deep learning offers the next major opportunity for specialist processors, Qualcomm's Karim Arabi claimed in his keynote at Mentor Graphics’ U2U in San Jose.
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