IEDM 2017


January 2, 2018

Watch out for layout effects on finFET reliability

As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.
Article  |  Topics: Blog - EDA  |  Tags: , , ,
December 6, 2017

European teams explore 3D integration tradeoffs

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations: ,
October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
May 15, 2017

IEDM opts for later deadline on 63rd conference

The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.

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