high level synthesis (HLS)


December 31, 2018

Closing code coverage with a hardware-aware HLS-to-RTL flow

Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
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July 30, 2018

HLS speeds up IP deployment at FotoNation

IP supplier FotoNation has decided to embrace the use of high-level synthesis in the creation of cores for smartphones and other high-integration, low-power systems.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , ,   |  Organizations:
May 11, 2015

Altera uses hierarchical approach to speed up FPGA compiles

Altera is revamping the Quartus II software for its FPGAs with a mapping and synthesis engine aimed at the upcoming Gen 10 products, as well as adding a C/C++ front-end for system-level design.
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February 25, 2015

Real Intent updates linter for aviation, Mathworks and SystemVerilog

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.
February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
January 5, 2015

Cadence high-level synthesis changes deal with congestion

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
May 24, 2014

Real Intent updates lint tool, adds Matlab and Simulink support

More lint rules, better SystemVerilog support, links to MATLAB and Simulink
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February 6, 2014

Cadence to buy Forte and build out HLS offering

EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
May 29, 2012

DAC 2012: Calypto brings tools together for high-level power savings

Calypto has combined the Catapult high-level synthesis (HLS) tool with elements of its PowerPro software to focus on the demand for lower-power SoC designs.

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