gate-level verification


February 11, 2019

DVCon USA 2019 preview: Mentor

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
February 27, 2017

Cadence tunes up simulators and FPGA prototyping

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.

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