formal verification

October 31, 2023

Accellera publishes draft of CDC standard

Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
November 15, 2022

Real Intent tool looks for glitches

Real Intent has developed a tool to check design and the potential for circuits to glitch.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
July 7, 2022

DAC 2022 preview: Axiomise

Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
March 2, 2022

Synopsys talks AI in verification at DVCon

Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
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December 3, 2021

Axiomise expands formal training services from beginner to expert

The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.
Article  |  Topics: Blog - EDA, - Training, Verification  |  Tags:   |  Organizations: ,
July 26, 2021

Learn how to apply formal verification to safety-critical aviation designs

A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Article  |  Topics: Verification  |  Tags: , , , , , , ,   |  Organizations:
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
March 18, 2021

DVCon to stick with virtual for Europe as US event highlights paper award

The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

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