The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
Machine learning is gradually moving into implementation and verification tools for EDA.
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
Free e-book offers an introduction to formal verification methods for those who may be curious about the technique, or who need to understand its advantages and limitations in order to manage its use effectively.
The formal verification specialist will be discussing its own experiences and has partnered with users for presentations at DVCon US.
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
Oski Technology will offer a range of daily presentations at its DAC 2017 and useful technical advice in the main conference program.
Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
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