finFET

June 21, 2018

Samsung couples EUV with DTCO for 7nm shrink

Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
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June 20, 2018

SAR-VCO combo tunes RF receiver power on 16nm

Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
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May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
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May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
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April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
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January 2, 2018

Watch out for layout effects on finFET reliability

As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.
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October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
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September 21, 2017

GlobalFoundries adds 12nm finFET process

GlobalFoundries intends to offer a 12nm FinFET process as a stepping stone from its 14nm process.
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June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
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June 18, 2017

Samsung 7nm uses EUV and split fin widths to push speeds

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
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