Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
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