In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.
Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.
The Liberty library format has been extended to cope with the most common forms of on-chip variation analysis in use today on nanometer processes.
Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
View All Sponsors