finFET

October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
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September 21, 2017

GlobalFoundries adds 12nm finFET process

GlobalFoundries intends to offer a 12nm FinFET process as a stepping stone from its 14nm process.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
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June 18, 2017

Samsung 7nm uses EUV and split fin widths to push speeds

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
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May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
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May 12, 2017

Advanced processes feature at VLSI in June

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
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December 12, 2016

IEDM explores faces of 3D monolithic integration

What will 3D integration look like? IEDM 2016 explored some of the options ranging from IoT sensors to advanced logic.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
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October 10, 2016

Speeding up AMS design in the age of finFETs

STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: ,
June 20, 2016

Let’s lose the fins

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,

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