finFET

March 11, 2015

Charting out the roadmap for FD-SOI

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,
March 10, 2015

Synopsys claims finFET leadership

Synopsys claims its tools have enabled 90% of finFET designs currently going into volume production
Article  |  Topics: Product  |  Tags:   |  Organizations: ,
December 18, 2014

Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL

The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
December 16, 2014

14nm/16nm finFETs debut at IEDM

The International Electron Device Meeting (IEDM) has once again provided a chance for the major chipmakers to go head-to-head with their latest processes - this time with finFETs.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , ,
November 24, 2014

A57 finFET design underlines routing challenges

In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
November 12, 2014

TSMC begins risk production of 16FF+

TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
November 12, 2014

Chip tariff eliminated and the big winner is… China?

Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
October 3, 2014

ARM tools take aim at finFET layout, timing issues

ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:
October 1, 2014

Liberty changes bring together nanometer OCV techniques

The Liberty library format has been extended to cope with the most common forms of on-chip variation analysis in use today on nanometer processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
August 19, 2014

Simulations point to better performance for Intel 14nm finFET

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors