finFET

July 25, 2014

GlobalFoundries licenses atomistic TCAD simulator toolchain

Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,
July 15, 2014

Cadence targets finFETs with RC extraction speedup

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
July 10, 2014

Startup claims recipe for ultimate finFET

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
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June 2, 2014

Samsung certifies Synopsys tools, IP at 14nm

Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Article  |  Topics: Conferences, Design to Silicon, Blog - IP  |  Tags: ,   |  Organizations: , ,
May 22, 2014

Pulsic opts for “layout early, layout often” strategy

Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
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April 15, 2014

Common Platform foundry alliance to be wound down

But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
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December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
November 20, 2013

FinFETs’ III-V future promises sub-7nm, RF and opto CMOS

FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: ,   |  Organizations:
November 13, 2013

TSMC succession plan emphasizes stability

TSMC stays the course with new co-CEOs as Morris Chang retains executive leadership for now while finFET, 3D and other new technologies settle in.
Article  |  Topics: Commentary, Design to Silicon  |  Tags: , , , , , , , ,   |  Organizations: , , ,

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