finFET

May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
May 12, 2017

Advanced processes feature at VLSI in June

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
December 12, 2016

IEDM explores faces of 3D monolithic integration

What will 3D integration look like? IEDM 2016 explored some of the options ranging from IoT sensors to advanced logic.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
October 10, 2016

Speeding up AMS design in the age of finFETs

STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , ,   |  Organizations: ,
June 20, 2016

Let’s lose the fins

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,
May 18, 2016

ARM completes multicore test chip on 10nm finFET

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations: ,
April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
March 30, 2016

Synopsys updates custom design tools for the finFET age

Synopsys is updating its custom design tools to make working with finFET based processes easier.
Article  |  Topics: Product  |  Tags: , ,   |  Organizations:
August 6, 2015

Flow exploration key to finFET network processor implementation

Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations: , ,

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