August 6, 2015

Flow exploration key to finFET network processor implementation

Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , ,   |  Organizations: , ,
July 30, 2015

10nm flow reveals complexity of finFET design process

Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Article  |  Topics: Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,
July 28, 2015

Samsung applies early prediction and color management to 10nm plans

Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
June 16, 2015

Collaboration let HiSilicon accelerate 16nm finFET plans

HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
June 11, 2015

Two-day app challenge results in RTL power analyzer

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
June 8, 2015

Altera boosts density and pipelining in finFET FPGA shift

Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations:
May 25, 2015

Shape a major choice for sub-10nm nanowire FETs

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
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May 11, 2015

VLSI Symposia delve into future process choices

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,
April 22, 2015

Mentor tool streamlines multi-corner parasitic extraction

Mentor Graphics has launched Calibre xACT, a tool that uses deterministic algorithms to extract parasitics from complex finFET and other nanometer processes.
March 11, 2015

Charting out the roadmap for FD-SOI

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , ,


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