February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 16, 2018

SPIE Advanced Lithography 2018 preview: Mentor

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , , , , , ,   |  Organizations: ,
June 18, 2017

Samsung 7nm uses EUV and split fin widths to push speeds

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 12, 2017

Advanced processes feature at VLSI in June

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
February 23, 2016

Directed self assembly may offer similar benefits to EUV, process modeling study says

Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
Article  |  Topics: Conferences  |  Tags: , , , ,   |  Organizations:
February 11, 2016

SPIE Advanced Lithography Preview: Mentor Graphics

The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.
October 9, 2015

IMEC 5nm test chip to explore EUV and SAQP litho options

IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
July 9, 2015

IBM and friends at 7nm: breakthrough or science project?

IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
September 11, 2014

TSMC: e-beam winning on cost over EUV for lithography

EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.
Article  |  Topics: Design to Silicon, Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,


Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors