EUV

October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Article  |  Topics: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,   |  Organizations: , ,
June 21, 2018

Samsung couples EUV with DTCO for 7nm shrink

Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 20, 2018

Micron sees NAND powering on as DRAM struggles

Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
Article  |  Topics: Blog - EDA, - Product  |  Tags: , ,   |  Organizations: ,
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 16, 2018

SPIE Advanced Lithography 2018 preview: Mentor

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , , , , , ,   |  Organizations: ,
June 18, 2017

Samsung 7nm uses EUV and split fin widths to push speeds

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
May 12, 2017

Advanced processes feature at VLSI in June

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: , ,
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
February 23, 2016

Directed self assembly may offer similar benefits to EUV, process modeling study says

Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
Article  |  Topics: Conferences  |  Tags: , , , ,   |  Organizations:

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