dummy fill

February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
May 22, 2012

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Article  |  Topics: Commentary, Design to Silicon, Blog - EDA, - Industry Blogs  |  Tags: , ,   |  Organizations:


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