DTCO

October 25, 2023

VLSI Symposium 2024 looks to bridge digital and physical

The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
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July 24, 2023

Backside power shows promise but more complex manufacturing

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
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April 13, 2023

Arm signs sub-2nm deal with Intel foundry operation

Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
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December 9, 2022

Imec adds MOL layer to potentially cut cell size 20%

Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
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July 5, 2022

Primarius adds to library-development lineup

Primarius Technologies is making additions to its portfolio of library-design and verification tools at DAC next week.
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August 23, 2021

IEDM 2021 publishes course schedule

Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.
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September 14, 2020

Aprisa team to be doubled after Mentor purchase

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
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July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
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August 16, 2018

IBM and Synopsys to apply DTCO to post-finFET process development

Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
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