Fusion core targets voice-activated devices
Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.
DSP
Synopsys adds vector DSP operations to ARC EM processor IP
Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
Altera finds a way to cheaper floating point in FPGAs
Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.
Synopsys launches single kit to optimize IP across PPA
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
OMG adopts portable image and signal processing libraries
The Object Management Group has adopted the Vector Signal and Image Processing Library (VSIPL) for C and VSIPL++ for C++ as standard specifications that it will manage and promote.
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