DSP

R&D multicore processor demonstrates programmable extensions for DSP.

Cadence has organized its machine-learning platforms into three families intended to cover a wide range of on-device AI applications.

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.

Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.

Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.

Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.

Ceva has developed its first processor architecture aimed squarely at deep learning.

Hit by the loss of major client Apple, Imagination Technologies plans to sell off its MIPS and Ensigma divisions. The move signals a shift away from previous plans to diversify out from graphics processors.

Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.