Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.
Ceva has developed its first processor architecture aimed squarely at deep learning.
Hit by the loss of major client Apple, Imagination Technologies plans to sell off its MIPS and Ensigma divisions. The move signals a shift away from previous plans to diversify out from graphics processors.
Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.
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