double patterning

August 18, 2014

Power and clocking at 20nm force changes in FPGAs

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
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July 10, 2014

Startup claims recipe for ultimate finFET

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
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June 3, 2014

Remember 20nm? Qualcomm does

Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
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March 26, 2014

Even EUV faces a 1D future, says IMEC

IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
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May 22, 2013

Gartner: Multi-patterning here to stay, EUV lithography still 50:50

Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
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March 20, 2013

DATE: Double patterning and finFETs force flexibility on tools

EDA companies are having to plan for the different ways in which double patterning and finFETs could move into fabs, Antun Domic of Synopsys explains.
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January 28, 2013

Cadence updates Virtuoso for the 20nm generation

Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
December 11, 2012

Semiconductor roadmap gets fuzzier at IEDM

Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
December 4, 2012

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
October 16, 2012

EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology

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