design security

May 20, 2015

Imagination to extend virtualization across the SoC

Imagination Technologies plans to introduce support for virtualization across all its processor cores, including signal processors such as the Ensigma family, as part of a plan to improve SoC security.
May 19, 2015

Tortuga introduces security checks for SoC designs

Startup Tortuga Logic has developed a toolkit for checking the security aspects of SoC hardware designs.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
May 13, 2015

ARM calls for Internet Protocol to the edge in security play

ARM CTO Mike Muller called for IP to be used throughout the IoT as part of a strategy for secure systems at a recent NMI seminar at Bletchley Park, England.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
April 21, 2015

Are you ready for design for crime?

Designers will need to take crime into account as part of their design signoff process, Wally Rhines argued in his keynote at Mentor Graphics' U2U San Jose 2015 conference.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
February 26, 2015

Embedded world wakes up to security

Unsettled by attacks on embedded devices such as the point-of-sale terminals used by retailers such as Target and the potential for hackers to target critical infrastructure, the industry focused squarely on security at this year’s Embedded World in Nürnberg, Germany.
June 5, 2014

EDA industry must look to new markets for growth – Rhines

New markets such as hardware cyber security, automotive and embedded software key to EDA industry growth
Article  |  Topics: Conferences, General  |  Tags: , ,   |  Organizations:
April 22, 2014

Cadence to expand formal portfolio with Jasper buy

Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations: ,
November 5, 2013

Formal app looks for sneak paths in secure chips

Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 9, 2013

Xilinx tapes out for first of 20nm-generation FPGAs

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
June 18, 2013

Microsemi focuses on security with Igloo2 FPGAs

Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , ,   |  Organizations:

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