September 10, 2015
UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
June 9, 2015
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
June 8, 2015
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
June 3, 2015
Technology from Duolog acquisition used to ease the configuration of interconnect, debug and trace - and the integration of third-party IP
May 21, 2015
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
April 28, 2015
Cadence Design Systems has launched a debug tool designed to improve the speed of bug hunting in SystemVerilog but which the company expects to grow into analog and post-silicon work.
April 22, 2015
UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
February 9, 2015
New portfolio integrates and extends existing industrial embedded tools to meet the demands of Industry 4.0
October 2, 2014
A multiprocessor test chip has led ARM to improve the energy-control strategy for its Big.Little architecture and to simplify the debug architecture for the company's multicore processor IP.
September 30, 2014
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.