debug

June 21, 2018

DAC 2018 preview: Real Intent

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
February 20, 2018

DVCon US 2018 preview: OneSpin Solutions

The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.
January 28, 2018

UltraSoC delivers trace for RISC-V

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
January 23, 2018

Triage without tears: improving debug’s most human challenge

Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , ,   |  Organizations:
October 17, 2017

Arm TechCon 2017 preview: Mentor

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
June 19, 2017

UltraSoc donates trace format to RISC-V group

UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: ,
April 28, 2017

ARM deploys data-center tech to study verification patterns

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,

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