The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
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