debug

October 17, 2017

Arm TechCon 2017 preview: Mentor

Mentor will present seven papers during the ARMTech Con and a dedicated session, and exhibit at Booth #606.
June 19, 2017

UltraSoc donates trace format to RISC-V group

UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: ,
April 28, 2017

ARM deploys data-center tech to study verification patterns

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations: ,
November 24, 2016

Codasip adopts UltrasSoC debug for RISC-V cores

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
Article  |  Topics: Blog - IP  |  Tags: ,   |  Organizations:
September 20, 2016

UltraSoC to support RISC-V

UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , ,   |  Organizations:
February 25, 2016

Mentor’s Veloce boasts emulation gains fueled by software

Mentor Graphics is looking to get yet more efficiency from its market-leading Veloce emulator family through an OS upgrade and new task-specific Apps.
December 1, 2015

Ultrasoc tweaks debug technology to act as SoC burglar alarm

Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , ,   |  Organizations:
November 11, 2015

UltraSoC adds CoreSight and Ceva debug support

UltraSoC is extending its debug support for a variety of processor cores through compatibility with ARM’s CoreSight debug system as well as support for Ceva’s DSP cores.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
September 16, 2015

Synopsys extends FPGA-based prototyping to 1.6bn ASIC gates

Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Article  |  Topics: Blog - IP, - Verification  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors