DAC 2013

June 7, 2013

FinFET shift could drive analog automation as layout effects bite

The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
June 4, 2013

Timing signoff: maybe it’s time to get rid of the clock

The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.
June 3, 2013

CMOS “good for another century,” says father of finFET

CMOS approaches are likely to underpin electronics for the next century, according to Chenming Hu, father of the finFET
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June 3, 2013

UPF group moves to consider system-power issues

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
June 3, 2013

Embedded world ‘needs EDA’s models’

The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.
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May 22, 2013

DAC 2013 Preview IX: Manufacturability

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
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May 22, 2013

DAC 2013 Preview VIII: Low-power design

Sessions at the DAC 2013 conference in Austin, Texas focus on low-power design and engineering low-energy systems from the system level down to physical.
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May 22, 2013

DAC 2013 Preview VII: Verification and simulation

DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.
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May 21, 2013

DAC 2013: The Gary Smith EDA ‘what to see’ list is live

Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.
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May 20, 2013

Cadence tackles timing signoff with Tempus

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.
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