Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
The 2012 Design Automation Conference took place in San Francisco at the beginning of June.
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
Intel's Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.
Foundries can’t hand down design rules on tablets of stone any more - success at 20nm will take close collaboration with customers and tool vendors
Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.
Could more flexible licensing strategies for cloud-based EDA enable more efficient simulation and a new wave of business models?
Can process migration tools help the yield-challenged and speed the path to 20nm?
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
Verification drives system-level adoption as sales leap 76%. Virtual prototyping is also on the rise but there are gaps in the tool-set.
What are the chances that FD SOI will become a mainstream process for future nodes?
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