clock domain crossing

June 21, 2018

DAC 2018 preview: Real Intent

Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
Article  |  Topics: Conferences, Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
May 26, 2016

Real Intent extends Meridian Constraints for untimed paths

Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
February 26, 2016

Six quick videos introduce key formal verification concepts

Videos discuss formal verification planning, correct initialisation, writing constraints, developing properties, interpreting results - and knowing when you have done enough.
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
September 30, 2014

Real Intent’s Meridian CDC flexes hierarchical muscle, adds flexible debug

Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations:
June 2, 2014

Real Intent’s Pranav Ashar on converging design and verification

Verify early and simulate as little as possible - the idea is familiar but how do you get there?
October 30, 2013

The prospects for GALS: Real Intent’s view

Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
September 5, 2013

Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: ,

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