Real Intent's move into post-synthesis CDC debug leads its DAC 2018 activities, with technical papers on its new Verix PhyCDC tool also now online for those who cannot make it.
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
Videos discuss formal verification planning, correct initialisation, writing constraints, developing properties, interpreting results - and knowing when you have done enough.
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Major overhaul of clock domain crossing suite adds configurable debugger, boosts performance by 30% and cuts memory 40% for 'giga-scale' designs.
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
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