cell-aware test

June 30, 2015

Chipmakers see 3x test-pattern saving in embedded-test logic

Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,
October 24, 2014

Synopsys combines cell-aware, slack-based test to find transient defects, adds eFlash support

Two approaches to greater reliability revealed in Synopsys ATPG and DesignWare updates
Article  |  Topics: Product, Tested Component to System  |  Tags: , , , ,   |  Organizations:


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