DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
New version of Vivado adds verification features and speed, extends Zynq support
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar
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