December 12, 2018
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
May 23, 2018
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
May 22, 2018
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
April 10, 2018
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
March 23, 2018
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
February 16, 2018
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
May 15, 2017
The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.
June 20, 2016
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
October 9, 2015
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
May 25, 2015
TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold