3DIC

October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Article  |  Topics: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,   |  Organizations: , ,
July 11, 2018

Leti and Soitec partner for wafer development

Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
May 22, 2018

IEDM 2018 aims to span quantum, neuromorphic and CMOS devices

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , ,   |  Organizations:
June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations: ,
May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations:
May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
January 9, 2017

VLSI Symposia issue calls for papers

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:

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