Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.
Microsemi has launched a family of non-volatile FPGAs that use a 28nm process to increase density over the previous SmartFusion devices.
Menta SAS has launched an embedded FPGA core family that improves density over previous versions.
According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
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