28nm

December 12, 2018

IEDM shows progress on embedded eMRAM

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
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July 12, 2018

With RF, power and MRAM, FD-SOI finds its role

FD-SOI is gradually building up a presence as a technology not just for low-power but RF and power integration.
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February 21, 2018

Bulk transistor design aims for near-threshold power cuts

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.
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February 14, 2017

Microsemi takes flash FPGAs to 28nm

Microsemi has launched a family of non-volatile FPGAs that use a 28nm process to increase density over the previous SmartFusion devices.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , ,   |  Organizations:
June 6, 2016

Menta launches fourth-generation embedded FPGA core

Menta SAS has launched an embedded FPGA core family that improves density over previous versions.
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December 11, 2015

IEDM keynote: cost scaling will swap architectural changes for area

According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
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September 14, 2015

Menta aims for TSMC 28nm with embedded FPGA cores

Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
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July 13, 2015

GlobalFoundries tunes 28nm for smaller, lower-power FD-SOI

GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
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June 10, 2015

TSMC adds Cadence and Imagination subsystems for IoT

Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
June 8, 2015

DTCO tool aims to squeeze more out of older processes

Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
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